Memory interface – a summary

The Cortex®-M3 and Cortex-M4 processors possess the following memory system features:

Memory interface - a summary knowledge operations to SRAM

4GB straight line address space – With 32-bit addressing, the ARM® processors have access to as much as 4GB of storage. Even though many embedded systems don’t need greater than 1MB of memory, the 32-bit addressing capacity ensures future upgrade and expansion options. The Cortex-M3 and Cortex-M4 processors provide 32-bit buses utilizing a generic bus protocol known as AHB LITE. Public transit enables connections to 32/16/8-bit memory devices with appropriate memory interface controllers.

Architecturally defined memory map – The 4GB storage is split into numerous regions for a number of predefined memory and peripheral uses. This enables the processor design to become enhanced for performance. For instance, the Cortex-M3 and Cortex-M4 processors have multiple bus interfaces to permit synchronised access in the CODE region for rule and knowledge operations to SRAM or peripheral regions.

Support for little endian and large endian memory systems – The Cortex-M4 and Cortex-M4 processors could work with either little endian or big endian memory systems. Used, a microcontroller method is normally made with only one endian configuration.

Memory interface - a summary some bufferable memory

Bit band accesses (optional) – Once the bit-band feature is incorporated (based on microcontroller/System-on-Nick vendors), two 1MB regions within the memory map are bit addressable via two bit-band regions. This enables atomic use of individual bits in SRAM or peripheral address space.

Write buffer – Whenever a write transfer to some bufferable memory region will require multiple cycles, the transfer could be buffered through the internal write buffer within the Cortex-M3 or Cortex-M4 processor so the processor could execute the following instruction, if at all possible. This enables greater program execution speed.

Memory Protection Unit (Optional) – The MPU is really a programmable unit which defines access permissions for a number of memory regions. The MPU within the Cortex-M3 and Cortex-M4 processor supports eight programmable regions, and could be combined with an embedded OS to supply a robust system.

Unaligned transfer support – All processors supporting ARMv7-M architecture (including Cortex-M3 and Cortex-M4 processors) support unaligned data transfers.


An Overview of Memory – Part 1 of 2 – CompTIA A+ 220-701