Attacking the memory bottleneck
Outdoors Coherent Accelerator Processor Interface (OpenCAPI), announced only at that week’s Flash Memory Summit, is managed through the OpenCAPI Consortium. It’s a brand new high-performance bus interface created for servers that presently has memory semantics by means of outdoors Memory Interface (OMI). The large distinction between it and also the standard memory interfaces for DRAM may be the switch from parallel to serial within the same fashion that PCI Express (PCIe) replaces the parallel PCI bus. The consortium was began by AMD, Google, IBM, Mellanox Technologies, and Micron.
This past year, IBM announced that new Power9 processors would incorporate an OpenCAPI interface for memory support. It will likely be interesting to find out if other processor and GPU vendors follow this route, however the advantages act like individuals of PCIe.
Microchip is the main thing on delivering on storage needs. The SMC 1000 8x25G PM8596 nick functions a front finish to memory utilizing an OMI interface (Fig. 1). One huge difference between your conventional parallel interface and also the serial OMI would be that the interface is platform agnostic. OMI comes with an abstraction layer therefore, a controller can affix to various kinds of media.
1. The SMC 1000 8x25G nick supports DDR4 DRAM memory while supplying a typical OMI serial interface.
Outdoors Coherent Accelerator Processor Interface (OpenCAPI), announced only at that week’s Flash Memory Summit, is managed through the OpenCAPI Consortium. It’s a brand new high-performance bus interface created for servers that presently has memory semantics by means of outdoors Memory Interface (OMI). The large distinction between it and also the standard memory interfaces for DRAM may be the switch from parallel to serial within the same fashion that PCI Express (PCIe) replaces the parallel PCI bus. The consortium was began by AMD, Google, IBM, Mellanox Technologies, and Micron.
This past year, IBM announced that new Power9 processors would incorporate an OpenCAPI interface for memory support. It will likely be interesting to find out if other processor and GPU vendors follow this route, however the advantages act like individuals of PCIe.
Microchip is the main thing on delivering on storage needs. The SMC 1000 8x25G PM8596 nick functions a front finish to memory utilizing an OMI interface (Fig. 1). One huge difference between your conventional parallel interface and also the serial OMI would be that the interface is platform agnostic. OMI comes with an abstraction layer therefore, a controller can affix to various kinds of media.
1. The SMC 1000 8x25G nick supports DDR4 DRAM memory while supplying a typical OMI serial interface.
The normal DDR4-3200 memory funnel requires over 300 pins and it has a bandwidth of 25 GB/s. Just one OMI memory funnel uses about 75 pins and may provide the same 25-GB/s throughput. The 4x OMI system employs comparable quantity of pins because the parallel interface, but it features a 100-GB/s bandwidth or perhaps an increase of the factor of 4.
Microchip’s SMC 1000 8x25G controller nick supports x4 and x8 interfaces with 25.6-Gb/s serial links using OIF-28G-MR support. Including dynamic low-power modes. Housed inside a 17- by 17-mm package, it may interface to NVDIMM-N persistent-memory modules in addition to a selection of 16-Gb DDR4 memory with as many as four ranks. The on-board, open-source firmware handles DDR/OMI initialization and offers in-band temperature and error monitoring support in addition to support for that ChipLink Graphical user interface.
The SMC 1000 8x25G provides security and knowledge-protection services, too. It may support hardware root-of-trust, secure boot, and secure update. Also incorporated is single-symbol-correction/double-symbol-recognition ECC support. The nick are designed for memory scrubbing with auto correction of errors.
The DDIMM form factor (Fig. 2) supplies a point-to-point 8x25G OMI memory interface. These DDIMMs support DDR4 DRAM memory. DDIMM modules can be found from numerous vendors, including SMART Modular, Samsung Electronics, and Micron, in multiple capacities from 16 GB as much as 256 GB.
2. This DDIMM form factor is made to support a variety of volatile and non-volatile storage chips.
While using OMI approach brings advantages by using it, for example greater bandwidth minimizing pin counts. Normally, load/store operations are queued through the memory controller inside the processor. Within this situation, the memory controller is integrated inside the SMC 1000 8x25G. Microchip’s product has innovated in device latency, so the improvement in latency between your older parallel DDR interface which newer OMI serial interface is under 4 ns in comparison with LRDIMM latency.
The OpenCAPI consortium makes the host and target OMI IP component technology open to consortium people on the royalty-free basis. This will further adoption, and so will processor, GPU, and FPGA implementations that make the most of it. Likewise, embedded applications might be ripe for this kind of interface, especially single-funnel implementations where reduced pin count could be beneficial. Computing around the edge is demanding more, greater-performance memory.
Resourse: https://electronicdesign.com/embedded-revolution/
