Ddr memory interface basics
Double data-rate (DDR) memory has ruled the roost because the primary system memory in Computers for any lengthy time. Recently, it’s seeing more usage in embedded systems too. Let us consider the fundamentals of the DDR interface after which transfer to physical-layer testing (see Figure 1).
Figure 1: An agent test setup for physical-layer DDR testing
Double data-rate (DDR) memory has ruled the roost because the primary system memory in Computers for any lengthy time. Recently, it’s seeing more usage in embedded systems too. Let us consider the fundamentals of the DDR interface after which transfer to physical-layer testing (see Figure 1).
Figure 1: An agent test setup for physical-layer DDR testing
A DDR interface entails each DRAM nick transferring data to/in the memory controller by way of several digital data lines. These data streams are supported with a strobe signal. Because data can flow both in the controller towards the DRAM (write operation) and in the DRAM towards the controller (read operation, these digital line is bi-directional anyway.
Common clock, command, and address lines serve all DRAM chips. Since these lines control the interface’s operation, they’re unidirectional between your controller and also the memory ICs. Figure 2 illustrates the “fly-by” topology being used starting with the DDR3 standard.
Figure 2: Common clock, command, and address lines link DRAM chips and controller
DDR is “double data rate” memory due to how data transfers are timed: a byte is transmitted around the rising fringe of the time, and the other around the falling fringe of the time. The time runs at 1 / 2 of the DDR data rate and it is given to all memory chips.
The DDR command bus includes several signals that control the whole process of the DDR interface. Command signals are clocked only around the rising fringe of the time. Possible command states vary by DDR speed grade but could include: deselect, no operation, read, write, bank activate, precharge, refresh, and mode register set.
The address bus selects which cells from the DRAM are now being written to or read from. Such as the command bus, the address bus is single-clocked. The part values around the bus determine the financial institution, row, and column being written or read.
Because of the interface’s bi-directional nature, information is transferred between your memory and controller in bursts. To that particular finish, the strobe (DQS) signal is really a differential “bursted clock” that just functions during read operations. In many DDR generations since its beginning, the timing relationship between your strobe and knowledge signals differs for reads and writes (see Figure 3).
Figure 3: The timing relationship between your DDR strobe and knowledge signals differs for reads and writes
Finally, each DRAM nick has multiple parallel data lines (DQ0, DQ1, and so forth) that carry data in the controller towards the DRAM for write operations and the other way around for read operations. The information signals are true double data-rate signals that transition in the same rate because the clock/strobe (two transfers per clock cycle).
About the writer:
David Maliniak became a member of Teledyne LeCroy this year after greater than 3 decades like a author/editor within the electronics Business to business press, many of which was spent at Electronic Design covering EDA and T&M. David earned a b -.A. in journalism from New You are able to College.
These details initially made an appearance around the Teledyne LeCroy Test Happens Blog.
Resourse: https://signalintegrityjournal.com/blogs/8-for-good-measure/publish/
