Synopsys and tsmc collaborate to build up interface, analog and foundation ip for 12-nm finfet process – marly 15, 2017
MOUNTAIN VIEW, Calif., March 15, 2017 /PRNewswire/ —
Highlights:
- DesignWare Interface IP portfolio for TSMC 12FFC process includes USB, DisplayPort, PCI Express, DDR, LPDDR, SATA, MIPI, Ethernet and HDMI
- 12-bit data converters rich in-performance SAR-based architecture deliver low power and small area
- Logic libraries, memory compilers and-Performance Core Design Kits enable entire SoC designs to become enhanced for speed and power consumption
Synopsys, Corporation. (Nasdaq: SNPS) today announced its collaboration with TSMC to build up DesignWare® Interface, Analog and Foundation IP for TSMC’s 12FFC process. By providing an array of IP on TSMC’s latest low-power process, Synopsys is enabling designers to benefit from the reduced leakage and small area the best-selling new process. Synopsys and TSMC have partnered on the introduction of Synopsys IP for advanced process technologies in excess of 2 decades, producing a robust portfolio of IP supporting process technologies lower to 7nm. Synopsys DesignWare IP for that 12FFC process enables designers to accelerate growth and development of mobile SoCs that contain logic libraries, embedded recollections, embedded make sure repair, USB 3.1/3./2., USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4X, PCI Express® 4./3.1/2.1, SATA 6G, HDMI 2., MIPI M-PHY and D-PHY and knowledge ripper tools IP.
“TSMC and Synopsys share a lengthy good reputation for supplying designers with an array of high-quality IP on TSMC’s advanced FinFET processes,” stated Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By developing IP around the latest TSMC 12FFC process, Synopsys is paving the way in which for designers to enhance their SoCs’ leakage minimizing immediate and ongoing expenses.”
“As SoCs still incorporate more complex functionality, designers are continually challenged with meeting aggressive performance, power and area needs,” stated John Koeter, v . p . of promoting for IP at Synopsys. “Our close collaboration with TSMC on the introduction of an extensive selection of IP for that 12FFC process will make sure that designers have timely accessibility high-quality, proven IP solutions they have to achieve their design goals and rapidly obtain product to promote.”
Availability
The DesignWare IP for USB 2./3./3.1/Type-C, DisplayPort, PCI Express 4./3./2., SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2., DDR4/3 and LPDDR4X, and 12-bit data converters are anticipated to be shown for TSMC’s 12FFC process in Q3 2017.
About DesignWare IP
Synopsys is really a leading provider of high-quality, plastic-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded recollections, embedded test, analog IP, wireless and wired interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Faster initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys’ extensive purchase of IP quality, comprehensive tech support team and powerful IP development methodology enables designers to lessen integration risk and accelerate time-to-market. For additional info on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
MOUNTAIN VIEW, Calif., March 15, 2017 /PRNewswire/ —
Highlights:
- DesignWare Interface IP portfolio for TSMC 12FFC process includes USB, DisplayPort, PCI Express, DDR, LPDDR, SATA, MIPI, Ethernet and HDMI
- 12-bit data converters rich in-performance SAR-based architecture deliver low power and small area
- Logic libraries, memory compilers and-Performance Core Design Kits enable entire SoC designs to become enhanced for speed and power consumption
Synopsys, Corporation. (Nasdaq: SNPS) today announced its collaboration with TSMC to build up DesignWare® Interface, Analog and Foundation IP for TSMC’s 12FFC process. By providing an array of IP on TSMC’s latest low-power process, Synopsys is enabling designers to benefit from the reduced leakage and small area the best-selling new process. Synopsys and TSMC have partnered on the introduction of Synopsys IP for advanced process technologies in excess of 2 decades, producing a robust portfolio of IP supporting process technologies lower to 7nm. Synopsys DesignWare IP for that 12FFC process enables designers to accelerate growth and development of mobile SoCs that contain logic libraries, embedded recollections, embedded make sure repair, USB 3.1/3./2., USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4X, PCI Express® 4./3.1/2.1, SATA 6G, HDMI 2., MIPI M-PHY and D-PHY and knowledge ripper tools IP.
“TSMC and Synopsys share a lengthy good reputation for supplying designers with an array of high-quality IP on TSMC’s advanced FinFET processes,” stated Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By developing IP around the latest TSMC 12FFC process, Synopsys is paving the way in which for designers to enhance their SoCs’ leakage minimizing immediate and ongoing expenses.”
“As SoCs still incorporate more complex functionality, designers are continually challenged with meeting aggressive performance, power and area needs,” stated John Koeter, v . p . of promoting for IP at Synopsys. “Our close collaboration with TSMC on the introduction of an extensive selection of IP for that 12FFC process will make sure that designers have timely accessibility high-quality, proven IP solutions they have to achieve their design goals and rapidly obtain product to promote.”
Availability
The DesignWare IP for USB 2./3./3.1/Type-C, DisplayPort, PCI Express 4./3./2., SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2., DDR4/3 and LPDDR4X, and 12-bit data converters are anticipated to be shown for TSMC’s 12FFC process in Q3 2017.
About DesignWare IP
Synopsys is really a leading provider of high-quality, plastic-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded recollections, embedded test, analog IP, wireless and wired interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Faster initiative offers IP prototyping kits, IP software development kits and IP subsystems. Synopsys’ extensive purchase of IP quality, comprehensive tech support team and powerful IP development methodology enables designers to lessen integration risk and accelerate time-to-market. For additional info on DesignWare IP, visit http://www.synopsys.com/designware.
About Synopsys
Synopsys, Corporation. (Nasdaq: SNPS) may be the Plastic to Software™ partner for innovative companies developing the electronic products and computer programs we depend on every single day. Because the world’s 15th largest software company, Synopsys includes a lengthy good reputation for as being a world leader in electronic design automation (EDA) and semiconductor IP and it is growing its leadership in software security and quality solutions. Whether you are a method-on-nick (SoC) designer creating advanced semiconductors, or perhaps a software developer writing applications that need the greatest security and quality, Synopsys has got the solutions required to deliver innovative, high-quality, secure products. Find out more at www.synopsys.com.
Forward-Searching Statements
This pr release contains forward-searching statements inside the concept of Section 21E from the Securities Exchange Act of 1934, including statements concerning the expected release and advantages of DesignWare IP for USB 2./3./3.1/Type-C, DisplayPort, PCI Express 4./3./2., SATA 6G, MIPI D-PHY/M-PHY, 25G Ethernet, HDMI 2., DDR4/3 and LPDDR4X, and 12-bit data converters. Any statements that aren’t statements of historic fact might be considered to become forward-searching statements. These statements involve known and unknown risks, uncertainties along with other factors that may cause actual results, periods or achievements to differ materially from individuals expressed or implied within the forward-searching statements. Other risks and uncertainties that could apply are positioned forth within the “Risks” portion of Synopsys’ most lately filed Annual Set of Form 10-K. Synopsys undertakes no obligation to update openly any forward-searching statements, in order to update the reason why actual results could differ materially from individuals anticipated during these forward-searching statements, even when new information opens up later on.
Editorial Contact:
Monica Marmie
Synopsys, Corporation.
650-584-2890
monical@synopsys.com
SOURCE Synopsys, Corporation.
Resourse: https://news.synopsys.com/
